Parallelization of motion compensation algorithm based on reconfigurable video array processor

doi:10.19682/j.cnki.1005-8885.2019.1029

中国邮电高校学报(英文版) ›› 2019, Vol. 26 ›› Issue (6): 83-93.doi: 10.19682/j.cnki.1005-8885.2019.1029

• Signal processing • 上一篇下一篇

Parallelization of motion compensation algorithm based on reconfigurable video array processor

Xie Xiaoyan, Lei Xiang, Zhou Jinna, Zhu Yun, Jiang Lin

1. School of Computer, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
2. School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
3. Integrated Circuit Design Laboratory, Xi'an University of Science and Technology, Xi'an 710054, China

收稿日期:2018-10-23 修回日期:2019-12-04 出版日期:2019-12-31 发布日期:2020-03-10
通讯作者: Xie Xiaoyan, E-mail: xxy@xupt.edu.cn E-mail:xxy@xupt.edu.cn
作者简介:Xie Xiaoyan, E-mail: xxy@xupt.edu.cn
基金资助:
This work was supported by the National Natural Science Foundation of China (61834005, 61772417, 61802304, 61874087, 61602377, 61634004, 61272120), the Shaanxi Province Coordination Innovation Project of Science and Technology (2016KTZDGY02-04-02), the Shaanxi Provincial Key R&D Plan (2017GY-060) and Shaanxi International Science and Technology Cooperation Program (2018KW-006).

Parallelization of motion compensation algorithm based on reconfigurable video array processor

Xie Xiaoyan, Lei Xiang, Zhou Jinna, Zhu Yun, Jiang Lin

1. School of Computer, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
2. School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
3. Integrated Circuit Design Laboratory, Xi'an University of Science and Technology, Xi'an 710054, China

Received:2018-10-23 Revised:2019-12-04 Online:2019-12-31 Published:2020-03-10
Contact: Xie Xiaoyan, E-mail: xxy@xupt.edu.cn E-mail:xxy@xupt.edu.cn
About author:Xie Xiaoyan, E-mail: xxy@xupt.edu.cn
Supported by:
This work was supported by the National Natural Science Foundation of China (61834005, 61772417, 61802304, 61874087, 61602377, 61634004, 61272120), the Shaanxi Province Coordination Innovation Project of Science and Technology (2016KTZDGY02-04-02), the Shaanxi Provincial Key R&D Plan (2017GY-060) and Shaanxi International Science and Technology Cooperation Program (2018KW-006).

摘要/Abstract

摘要：

The new encoding tools of high efficiency video coding (HEVC) make the interpolation operation more complex in motion compensation (MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16 x 16 processor element (PE)'s array is used to dynamically process a 4 x 4 - 64 x 64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.

关键词: HEVC, MC, parallelization, reconfigurable

Abstract:

Key words: HEVC, MC, parallelization, reconfigurable

中图分类号:

TP39

Xie Xiaoyan, Lei Xiang, Zhou Jinna, Zhu Yun, Jiang Lin.

Parallelization of motion compensation algorithm based on reconfigurable video array processor

[J]. The Journal of China Universities of Posts and Telecommunications, 2019, 26(6): 83-93.

参考文献

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Parallelization of motion compensation algorithm based on reconfigurable video array processor

Parallelization of motion compensation algorithm based on reconfigurable video array processor

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