The Journal of China Universities of Posts and Telecommunications ›› 2024, Vol. 31 ›› Issue (2): 62-71.doi: 10.19682/j.cnki.1005-8885.2024.00010

Special Issue: 集成电路

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Design of digital calibration based on variable step size of sub-binary SAR ADC


  • Received:2023-12-04 Revised:2024-02-27 Online:2024-04-30 Published:2024-04-30
  • Supported by:
    Natural Science Basic Research Project of Shaanxi Province, China


Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter (SAR ADC), a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed. The least mean square (LMS) calibration algorithm was employed with a ramp signal used as the calibration input signal. Weight errors, extracted under injected disturbances, underwent iterative training to optimize weight values. To address the trade-off between conversion accuracy and speed caused by a fixed step size,  a novel variable step size algorithm tailored for SAR ADC calibration was propased. The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor manufacturing Company (TSMC) 0.35 μm complementary metal-oxide-semiconductor (CMOS) commercial process. Simulation of the SAR ADC calibration algorithm was conducted using Simulink, demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation. The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size, also yielding a lower mean square error (MSE). After calibration, the simulation results for the SAR ADC exhibited an effective number of bit (ENOB) of 11.79 bit and a signal-to-noise and distortion ratio (SNDR) of 72.72 dB, signifying a notable enhancement in the SAR ADC performance.

Key words: SAR ADC, variable step size, digital calibration, disturbance technique