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Special Issue on Integrated circuit

  • Special Issue on Integrated circuit

    Integrated circuits (ICs) have become the cornerstone of the information age, driving scientific and technological revolutions and symbolizing strategic national competitiveness. With the continuous adjustment of economic structure and the changing of international relationships, the pivotal role of ICs and related sectors has become increasingly prominent. To address Chinese critical “bottleneck” challenges in this domain, it is necessary to strengthen the research on semiconductor devices, IC design, and manufacturing technologies.

    To showcase the latest research progress and practice of Chinese scholars in the field of IC, and to promote the development of related research directions, we have organized this Special Issue on Integrated Circuit. From the open call for submissions, we have selected 12 high-quality papers that cover the latest findings in semiconductor devices, IC design, high-performance computing and architectures. These papers reflect the latest research progress in the field of IC, and we hope that they can inspire more research work from related researchers. 

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    Superjunction 4H-SiC trench-gate IGBT with an integrated clamping PN diode
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 3-9.   DOI: 10.19682/j.cnki.1005-8885.2024.0001
    Abstract117)      PDF(pc) (4079KB)(71)       Save

    In this paper, a novel superjunction 4H-silicon carbide (4H-SiC) trench-gate insulated-gate bipolar transistor (IGBT) featuring an integrated clamping PN diode between the P-shield and emitter (TSD-IGBT) is designed and theoretically studied. The heavily doping superjunction layer contributes to a low specific on-resistance, excellent electric field distribution, and quasi-unipolar drift current. The anode of the clamping diode is in floating contact with the P-shield. In the on-state, the potential of the P-shield is raised to the turn-on voltage of the clamping diode, which prevents the hole extraction below the N-type carrier storage layer (NCSL). Additionally, during the turn-off transient, once the clamping diode is turned on, it also promotes an additional hole extraction path. Furthermore, the potential dropped at the semiconductor near the trench-gate oxide is effectively reduced in the off-state.

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    Trench gate GaN IGBT with controlled hole injection efficiency

    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 10-16.   DOI: 10.19682/j.cnki.1005-8885.2024.0012
    Abstract90)      PDF(pc) (2095KB)(53)       Save

    In this paper, a novel trench gate gallium nitride insulated gate bipolar transistor (GaN IGBT), in which the collector is divided into multiple regions to control the hole injection efficiency, is designed and theoretically studied. The incorporation of a P+/P- multi-region alternating structure in the collector region mitigates hole injection within the collector region. When the device is in forward conduction, the conductivity modulation effect results in a reduced storage of carriers in the drift region. As a result, the number of carriers requiring extraction during device turn-off is minimized, leading to faster turn-off speed. The results illustrate that the GaN IGBT with controlled hole injection efficiency (CEH GaN IGBT) exhibits markedly enhanced performance compared to conventional GaN IGBT, showing a remarkable 42.2% reduction in turn-off time and a notable 28.5% decrease in turn-off loss.

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    Performance study of vertical MSM solar-blind photodetectors based on β-Ga 2O 3 thin film
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 17-27.   DOI: 10.19682/j.cnki.1005-8885.2024.0006
    Abstract102)      PDF(pc) (4363KB)(47)       Save

    In this work, β-Ga2O3 thin films were grown on SiO2 substrate by atomic layer deposition (ALD) and annealed in N2 atmosphere to enhance the crystallization quality of the thin films, which were verified from X-rays diffraction (XRD). Based on the grown β-Ga2O3 thin films, vertical metal-semiconductor-metal (MSM) interdigital photodetectors (PDs) were fabricated and investigated. The PDs have an ultralow dark current of 1.92 pA, ultra-high photo-to-dark current ratio (PDCR) of 1.7×106, and ultra-high detectivity of 4.25×1014 Jones at a bias voltage of 10 V under 254 nm deep ultraviolet (DUV). Compared with the horizontal MSM PDs under the same process, the PDCR and detectivity of the fabricated vertical PDs are increased by 1 000 times and 100 times, respectively. In addition, the vertical PDs possess a high responsivity of 34.24 A/W and an external quantμm efficiency of 1.67×104%, and also exhibit robustness and repeatability, which indicate excellent performance. Then the effects of electrode size and external irradiation conditions on the performance of the vertical PDs continued to be investigated.

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      Preparation and characteristic study of Schottky diodes based on Ga2O3 thin films
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 28-37.   DOI: 10.19682/j.cnki.1005-8885.2024.0007
    Abstract88)      PDF(pc) (3625KB)(32)       Save
    This study uses atomic layer deposition (ALD) to grow Ga 2O 3 films on SiO 2 substrates and investigates the influence of film thickness and annealing temperature on film quality. Schottky diode devices are fabricated based on the grown Ga 2O 3 films, and the effects of annealing temperature, electrode size, and electrode spacing on the electrical characteristics of the devices are studied. The results show that as the film thickness increases, the breakdown voltage of the fabricated devices also increases. A Schottky diode with a thickness of 240 nm can achieve a reverse breakdown voltage of 300 V. The film quality significantly improves as the annealing temperature of the film increases. At a voltage of 5 V, the current of the film annealed at 900°C is 64 times that of the film annealed at 700°C. The optimum annealing temperature for Ohmic contact electrodes is 450°C. At 550°C, the Ohmic contact metal tends to burn, and the performance of the device is reduced. Reducing the electrode spacing increases the forward current of the device but decreases the reverse breakdown voltage. Increasing the Schottky contact electrode size increases the forward current, but the change is not significant, and there is no significant change in the reverse breakdown voltage. The device also performs well at high temperatures, with a reverse breakdown voltage of 220 V at 125°C.
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    50-110 GHz, high isolation, and high-power linearity single-pole double-throw switch utilizing  100-nm GaN HEMT technology
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 38-43.   DOI: 10.19682/j.cnki.1005-8885.2024.0011
    Abstract82)      PDF(pc) (2721KB)(21)       Save

    This article presents the design and performance of a single-pole double-throw (SPDT) switch operating in 50–110 GHz. The switch is fabricated in a 100-nm GaN high-electron-mobility transistors(HEMT) technology. To realize high-power capability, the dimensions of GaN HEMTs are selected by simulation verification. To enhance the isolation, an improved structure of shunt HEMT with two ground holes is employed. To extend the operation bandwidth, the SPDT switch with multi section resonant units is proposed and analyzed. To verify the SPDT switch design, a prototype operating in 50–110 GHz is fabricated. The measured results show that the fabricated SPDT switch monolithic microwave integrated circuit (MMIC) achieves an input 1 dB compression point (P1dB) of 38 dBm at 94 GHz, and an isolation within the range of 33 dB to 54 dB in 50–110 GHz. The insertion loss of the switch is less than 2.1 dB, while the voltage standing wave ratios (VSWR) of the input port and output port are both less than 1.8 in the operation bandwidth. Based on the measured results, the presented SPDT switch MMIC demonstrates high power capability and high isolation compared with other reported millimeter-wave SPDT MMIC designs.

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    All-dielectric terahertz metasurface governed by bound states in the continuum with high-Q factor
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 44-54.   DOI: 10.19682/j.cnki.1005-8885.2024.0003
    Abstract91)      PDF(pc) (3460KB)(25)       Save
    The method of terahertz (THz) resonance with a high-quality (high-Q) factor offers a vital physical mechanism for metasurface sensors and other high-Q factor applications. However, it is challenging to excite the resonance with a high-Q factor in metasurfaces with proper sensitivity as well as figure of merit (FOM) values. Here,  an all-dielectric metasurface composed of two asymmetrical rectangular blocks is suggested. Quartz and silicon are the materials applied for the substrate and cuboids respectively. The distinct resonance governed by bound states in the continuum (BIC) is excited by forming an asymmetric cluster by a novel hybrid method of cutting and moving the cuboids. The investigation focuses on analyzing the transmission spectra of the metasurface under different variations in structural parameters and the loss of silicon refractive index. When the proposed defective metasurface serves as a transmittance sensor, it shows a Q factor of 1.08×10 4 and achieves a FOM up to 4.8×10 6, which is obtained under the asymmetric parameter equalling 1 μm. Simultaneously, the proposed defective metasurface is sensitive to small changes in refractive index. When the thickness of the analyte is 180 μm, the sensitivity reaches a maximum value of 578 GHz / RIU. Hence, the proposed defective metasurface exhibits an extensive number of possible applications in the filters, biomedical diagnosis, security screening, and so on.
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    Design of high frequency broadband low insertion loss SAW filter at 3.5 GHz

    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 55-61.   DOI: 10.19682/j.cnki.1005-8885.2024.0004
    Abstract63)      PDF(pc) (2226KB)(37)       Save
    With the wide application of the fifth-generation mobile communication system (5G) technology, wireless communication equipment tends to develop in miniaturization, high frequency , and low loss. In this paper, a surface acoustic wave (SAW) filter with a center frequency of 3.5 GHz was designed. Firstly, the acoustic waveguide structure of the longitudinal leaky SAW (LLSAW) excitation is determined, and the two-dimensional (2D) theoretical model of the device is established by COMSOL Multiphysics. Secondly, the influence of electrode parameters on the performance of the device is studied, and the electrode parameters are optimized on this basis. By setting the device structure parameters reasonably, the spurious in the passband can be effectively suppressed. Finally, the center frequency of the mirror T-structure LLSAW filter is 3.536 GHz, the insertion loss is -1.414 dB, the bandwidth of -3 dB is 276 MHz, and the out-of-band rejection is greater than -30 dB.
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    Design of digital calibration based on variable step size of sub-binary SAR ADC
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 62-71.   DOI: 10.19682/j.cnki.1005-8885.2024.00010
    Abstract79)      PDF(pc) (5060KB)(20)       Save
    Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter (SAR ADC), a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed. The least mean square (LMS) calibration algorithm was employed with a ramp signal used as the calibration input signal. Weight errors, extracted under injected disturbances, underwent iterative training to optimize weight values. To address the trade-off between conversion accuracy and speed caused by a fixed step size,  a novel variable step size algorithm tailored for SAR ADC calibration was propased. The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor manufacturing Company (TSMC) 0.35 μm complementary metal-oxide-semiconductor (CMOS) commercial process. Simulation of the SAR ADC calibration algorithm was conducted using Simulink, demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation. The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size, also yielding a lower mean square error (MSE). After calibration, the simulation results for the SAR ADC exhibited an effective number of bit (ENOB) of 11.79 bit and a signal-to-noise and distortion ratio (SNDR) of 72.72 dB, signifying a notable enhancement in the SAR ADC performance.
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    Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 72-84.   DOI: 10.19682/j.cnki.1005-8885.2024.0005
    Abstract63)      PDF(pc) (3255KB)(20)       Save
    To apply a quasi-cyclic low density parity check (QC-LDPC) to different scenarios, a data-driven pipelined macro-instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm. The data-level parallelism is improved by instructions to dynamically configuring the multi-core computing units. Simultaneously, an intelligent adjustment strategy based on programmable wake-up controller (WuC) is designed so that the computing mode, operating voltage, and frequency of the QC-LDPC algorithm can be adjusted. This adjustment can improve the computing efficiency of the processor. The QC-LDPC decoders are verified on the Xilinx ZCU102 Field Programmable Gate Array (FPGA) board and the computing efficiency is measured. The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency. The maximum efficiency can reach up to 12.18 Mbit(s·mW) -1, which is more flexible than existing state-of-the-art processor for QC-LDPC.
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    Predicting stability of integrated circuit test equipment using  upper side boundary values of normal distribution
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 85-93.   DOI: 10.19682/j.cnki.1005-8885.2024.0002
    Abstract83)      PDF(pc) (473KB)(29)       Save
    In response to the growing complexity and performance of Integrated Circuit (IC), there is an urgent need to enhance the testing and stability of IC test equipment. A method was proposed to predict equipment stability using the upper side boundary value of normal distribution. Initially, the K-means clustering algorithm classifies and analyzes sample data. The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold. A range is then defined to categorize unqualified test data. Through experimental verification, the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value, which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.
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    Design and implementation of a multi-tile parallel scanning rasterization accelerator
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 94-104.   DOI: 10.19682/j.cnki.1005-8885.2024.0009
    Abstract82)      PDF(pc) (6311KB)(24)       Save
    In the design of a graphic processing unit (GPU), the processing speed of triangle rasterization is an important factor that determines the performance of the GPU. An architecture of a multi-tile parallel-scan rasterization accelerator was proposed in this paper. The accelerator uses a bounding box algorithm to improve scanning efficiency. It rasterizes multiple tiles in parallel and scans multiple lines at the same time within each tile. This highly parallel approach drastically improves the performance of rasterization. Using 65nm process standard cell library of Semiconductor Manufacturing International Corporation (SMIC), the accelerator can be synthesized to a maximum clock frequency of 220MHz. An implementation on the Genesys2 field programmable gate array (FPGA) board fully verifies the functionality of the accelerator. The implementation shows a significant improvement in rendering speed and efficiency and proves its suitability for high- performance rasterization.
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    Convolutional neural network adaptation and optimization method in SIMT computing mode
    zhenfu Feng Ya-Ying ZHANG Lele Yang Li-Dong XING
    The Journal of China Universities of Posts and Telecommunications    2024, 31 (2): 105-112.   DOI: 10.19682/j.cnki.1005-8885.2024.0008
    Abstract85)      PDF(pc) (3090KB)(32)       Save
    For studying and optimizing the performance of general-purpose computing on graphics processing units(GPGPU) based on single instruction multiple threads(SIMT) processor about the neural network application, this work contributes a self-developed SIMT processor named Pomelo and correlated assembly program. The parallel mechanism of SIMT computing mode and self-developed Pomelo processor is briefly introduced. A common convolutional neural network(CNN) is built to verify the compatibility and functionality of the Pomelo processor. CNN computing flow with task level and hardware level optimization is adopted on the Pomelo processor. A specific algorithm for organizing a Z-shaped memory structure is developed, which addresses reducing memory access in mass data computing tasks. Performing the above-combined adaptation and optimization strategy, the experimental result illustrates that reducing memory access in SIMT computing mode plays a crucial role in improving performance. A 6.52 times performance is achieved on 4 processing elements case.
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