Energy-efficient reconfigurable processor for QC-LDPC
via adaptive coding-voltage-frequency tuning

doi:10.19682/j.cnki.1005-8885.2024.0005

中国邮电高校学报(英文) ›› 2024, Vol. 31 ›› Issue (2): 72-84.doi: 10.19682/j.cnki.1005-8885.2024.0005

所属专题：集成电路

• IC and System Design • 上一篇下一篇

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

常立博¹,胡怡青¹,杜慧敏¹,王继禾²

1. 西安邮电大学
2. 西北工业大学

收稿日期:2023-11-30 修回日期:2024-03-09 出版日期:2024-04-30 发布日期:2024-04-30
通讯作者: 杜慧敏 E-mail:fv@xupt.edu.cn

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

Received:2023-11-30 Revised:2024-03-09 Online:2024-04-30 Published:2024-04-30
Contact: Hui-Min DU E-mail:fv@xupt.edu.cn

摘要/Abstract

摘要： To apply a quasi-cyclic low density parity check (QC-LDPC) to different scenarios, a data-driven pipelined macro-instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm. The data-level parallelism is improved by instructions to dynamically configuring the multi-core computing units. Simultaneously, an intelligent adjustment strategy based on programmable wake-up controller (WuC) is designed so that the computing mode, operating voltage, and frequency of the QC-LDPC algorithm can be adjusted. This adjustment can improve the computing efficiency of the processor. The QC-LDPC decoders are verified on the Xilinx ZCU102 Field Programmable Gate Array (FPGA) board and the computing efficiency is measured. The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency. The maximum efficiency can reach up to 12.18 Mbit(s·mW)^-1, which is more flexible than existing state-of-the-art processor for QC-LDPC.

关键词:

Abstract:

To apply a quasi-cyclic low density parity check (QC-LDPC) to different scenarios, a data-driven pipelined macro-instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm. The data-level parallelism is improved by instructions to dynamically configuring the multi-core computing units. Simultaneously, an intelligent adjustment strategy based on programmable wake-up controller (WuC) is designed so that the computing mode, operating voltage, and frequency of the QC-LDPC algorithm can be adjusted. This adjustment can improve the computing efficiency of the processor. The QC-LDPC decoders are verified on the Xilinx ZCU102 Field Programmable Gate Array (FPGA) board and the computing efficiency is measured. The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency. The maximum efficiency can reach up to 12.18 Mbit(s·mW)^-1, which is more flexible than existing state-of-the-art processor for QC-LDPC.

Key words: QC-LDPC, dynamic voltage and frequency scaling (DVFS), reconfigurable computing, coarse-grained reconfigurable arrays (CGRAs)

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Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

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