The Journal of China Universities of Posts and Telecommunications ›› 2024, Vol. 31 ›› Issue (2): 72-84.doi: 10.19682/j.cnki.1005-8885.2024.0005

Special Issue: 集成电路

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Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning


  • Received:2023-11-30 Revised:2024-03-09 Online:2024-04-30 Published:2024-04-30
  • Contact: Hui-Min DU


To apply a quasi-cyclic low density parity check (QC-LDPC) to different scenarios, a data-driven pipelined macro-instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm. The data-level parallelism is improved by instructions to dynamically configuring the multi-core computing units. Simultaneously, an intelligent adjustment strategy based on programmable wake-up controller (WuC) is designed so that the computing mode, operating voltage, and frequency of the QC-LDPC algorithm can be adjusted. This adjustment can improve the computing efficiency of the processor. The QC-LDPC decoders are verified on the Xilinx ZCU102 Field Programmable Gate Array (FPGA) board and the computing efficiency is measured. The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency. The maximum efficiency can reach up to 12.18 Mbit(s·mW)-1, which is more flexible than existing state-of-the-art processor for QC-LDPC.

Key words: QC-LDPC, dynamic voltage and frequency scaling (DVFS), reconfigurable computing, coarse-grained reconfigurable arrays (CGRAs)