Design of high parallel CNN accelerator based on FPGA for AIoT

doi:10.19682/j.cnki.1005-8885.2022.0026

The Journal of China Universities of Posts and Telecommunications ›› 2022, Vol. 29 ›› Issue (5): 1-9.doi: 10.19682/j.cnki.1005-8885.2022.0026

Special Issue: Special Topic on Artificial Intelligence of Things

Design of high parallel CNN accelerator based on FPGA for AIoT

Lin Zhijian¹,², Gao Xuewei¹, Chen Xiaopei¹, Zhu Zhipeng¹, Du Xiaoyong¹, Chen Pingping²

1.
2. SCHOOL OFADVANCED MANUFACTURING
3. Fuzhou University School of Advanced Manufacturing
4. Fuzhou University Advanced Manufacturing Academy

Received:2022-05-31 Revised:2022-09-08 Online:2022-10-31 Published:2022-10-28

Abstract

Abstract:

To tackle the challenge of applying convolutional neural network (CNN) in field-programmable gate array (FPGA) due to its computational complexity, a high-performance CNN hardware accelerator based on Verilog hardware description language was designed, which utilizes a pipeline architecture with three parallel dimensions including input channels, output channels, and convolution kernels. Firstly, two multiply-and-accumulate (MAC) operations were packed into one digital signal processing (DSP) block of FPGA to double the computation rate of the CNN accelerator. Secondly, strategies of feature map block partitioning and special memory arrangement were proposed to optimize the total amount of off-chip access memory and reduce the pressure on FPGA bandwidth. Finally, an efficient computational array combining multiplicative-additive tree and Winograd fast convolution algorithm was designed to balance hardware resource consumption and computational performance. The high parallel CNN accelerator was deployed in ZU3EG of Alinx, using the YOLOv3-tiny algorithm as the test object. The average computing performance of the CNN accelerator is 127.5 giga operations per second (GOPS). The experimental results show that the hardware architecture effectively improves the computational power of CNN and provides better performance compared with other existing schemes in terms of power consumption and the efficiency of DSPs and block random access memory (BRAMs).

Key words: artificial intelligence of things (AIoT)|convolutional neural network (CNN) accelerator|Winograd convolution| field-programmable gate
array (FPGA)

Lin Zhijian Gao Xuewei Chen Xiaopei Zhu Zhipeng Du Xiaoyong Chen Pingping. Design of high parallel CNN accelerator based on FPGA for AIoT[J]. The Journal of China Universities of Posts and Telecommunications, 2022, 29(5): 1-9.

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Design of high parallel CNN accelerator based on FPGA for AIoT

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