1. Elbaz R, Torres L, Sassatelli G, et al. Hardware engines for bus encryption: a survey of existing techniques. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05): Vol. 3, Mar 7-11, 2005, Munich, Germany. Piscataway, NJ, USA: IEEE, 2005: 40-45
2. Hennessy J L, Patterson D A. Computer architecture: a quantitative approach. 3rd ed. San Fransisco, CA, USA: Morgan Kaufmanm, 2003
3. Keating M, Flynn D, Aitken R, et al. Low power methodology manual for system-on-chip design. Berlin, Germany: Springer-Verlag, 2007
4. Suh G E, Clarke D, Gassend B, et al. Efficient memory integrity verification and encryption for secure processors. Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36’03), Dec 3-5, 2003, San Diego, CA, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2003: 339-350
5. Yang J, Gao L, Zhang Y T. Improving memory encryption performance in secure processors. IEEE Transactions on Computers, 2005, 54(5): 630-640
6. Platte J, Naroska E, Grundmann K. A cache design for a security architecture for microprocessors (SAM). Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS’06), Mar 13-16, 2006, Frankfurt, Germany. LNCS 3894. Berlin. Germany: Springer-Verlag, 2006: 435-449
7. Duc G, Keryell R. CryptoPage: an efficient secure architecture with memory encryption, integrity and information leakage protection. Proceedings of the 22nd Annual Computer Security Application Conference (ACSAC’06), Dec 11-15, 2006, Miami, FL, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 483-492
8. Gassend B, Suh G E, Clarke D, et al. Caches and Hash trees for efficient memory integrity verification. Proceedings of the 9th International Symposium on High-performance Computer Architecture (HPCA’03), Feb 8-12, 2003, Anaheim, CA, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2003: 295-306
9. Frankel S, Glenn R, Kelly S. The AES-CBC cipher algorithm and its use with IPsec. IETF RFC3602. 2003
10. Shi W D, Lee H S. Accelerating memory decryption and authentication with frequent value prediction. Proceedings of the 4th International Conference on Computing Frontiers (CF’07), May 7-9, 2007, Ischia, Italy. New York, NY, USA: ACM, 2007: 35-46
11. Yan C Y, Rogers B, Englender D, et al. Improving cost, performance, and security of memory encryption and authentication. Proceedings of the 33rd International Symposium on Computer Architecture (ISCA’06), Jun 17-21, 2006, Boston, MA, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 179-190
12. Anderson R, Kuhn M. Tamper resistance - A cautionary note. Proceedings of the 2nd USENIX Workshop on Electronic Commerce (EC’96), Nov 18-21, 1996, Oakland, CA, USA. New York, NY, USA: ACM, 1996: 1-11
13. Kuhn M G. Cipher instruction search attack on the bus-encryption security microcontroller DS5002FP. IEEE Transaction on Computer, 1998, 47(10): 1153-1157
14. Stallings W. Cryptography and network security: Principles and practices. 4th ed. Upper Saddle River, NJ, USA: Prentice Hall, 2006
15. Austin T, Larson E, Ernst D. SimpleScalar: an infrastructure for computer system modeling. Computer, 2002, 35(2): 59-67
16. Guthaus M R, Ringenberg J S, Ernst D, et al. MiBench: a free, commercially representative embedded benchmark suite. Proceedings of the IEEE 4th Annual Workshop on Workload Characterization (WWC’01), Dec 2, 2001, Austin, TX , USA. Piscataway, NJ, USA: IEEE, 2001: 3-14 |