Acta Metallurgica Sinica(English letters) ›› 2007, Vol. 14 ›› Issue (4): 104-109.doi: 1005-8885 (2007) 04-0104-06

• Wireless • Previous Articles     Next Articles

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

ZENG Yong-hong; ZOU Xue-cheng; LIU Zheng-lin; LEI Jian-ming   

  1. Research Center for VLSI and Systems, Department of Electronic Science and Technology, Huazhong University of Science and Technology
  • Received:2006-12-25 Revised:1900-01-01 Online:2007-12-24
  • Contact: ZENG Yong-hong


The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues: power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((24))2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property (IP) core for the wireless sensor node chips.

Key words:

WSN; rijindael algorithm; S-box; clock-less; composite field arithmetic; four-phase micropipeline