The Journal of China Universities of Posts and Telecommunications ›› 2021, Vol. 28 ›› Issue (2): 14-23.doi: 10.19682/j.cnki.1005-8885.2021.1002

Previous Articles     Next Articles

Statistical static timing analysis for circuit aging prediction 

Duan Shengyu, Zhai Dongyao, Lu Yue   

  1. 1. Shanghai Engineering Research Center of Intelligent Computing System, Shanghai University, Shanghai 200444, China
    2. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
    3. School of Electronics and Computer Science, University of Southampton, Southampton, UK

  • Received:2020-09-01 Revised:2020-12-08 Online:2021-04-30 Published:2021-04-30
  • Contact: Lu Yue

Abstract: Complementary metal oxide semiconductor ( CMOS) aging mechanisms including bias temperature instability
( BTI) pose growing concerns about circuit reliability. BTI results in threshold voltage increases on CMOS
transistors, causing delay shifts and timing violations on logic circuits. The amount of degradation is dependent on
the circuit workload, which increases the challenge for accurate BTI aging prediction at the design time. In this
paper, a BTI prediction method for logic circuits based on statistical static timing analysis (SSTA) is proposed,
especially considering the correlation between circuit workload and BTI degradation. It consists of a training phase,
to discover the relationship between circuit scale and the required workload samples, and a prediction phase, to
present the degradations under different workloads in Gaussian probability distributions. This method can predict
the distribution of degradations with negligible errors, and identify 50% more BTI-critical paths in an affordable
time, compared with conventional methods.

Key words: bias temperature instability (BTI), reliability, prediction, statistical static timing analysis (SSTA) 

CLC Number: