The Journal of China Universities of Posts and Telecommunications ›› 2020, Vol. 27 ›› Issue (2): 65-71.doi: 10.19682/j.cnki.1005-8885.2020.1008

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PPAA: a parallel primitive assembly accelerator in graphics processor

Deng Junyong, Xie Xiaoyan, Liu Yang, Tian Pu   

  1. 1. School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
    2. School of Computer, Xi'an University of Posts and Telecommunications, Xi'an 710121, China
  • Received:2018-08-20 Revised:2020-05-10 Online:2020-04-30 Published:2020-07-07
  • Contact: Deng Junyong, E-mail:
  • About author:Deng Junyong, E-mail:
  • Supported by:
    This work was supported by National Natural Science Foundation of China (61834005, 61772417, 61602377, 61802304, 61874087), Shaanxi International Science and Technology Cooperation Program (2018KW-006), Shaanxi Province Co-ordination Innovation Project of Science and Technology (2016KTZDGY02-04-02), Shaanxi Provincial Key R&D Plan (2017GY-060).

Abstract: Primitive assembly is an inevitable procedure of graphics rendering which performs the objects preparation for the following steps, however, the conventional approaches suffer from some issues, such as the missing of surface attribute, mismatch of color mode for clipped primitives, and performance bottleneck of rendering pipeline. This paper takes all these issues into considerations, and proposes a parallel primitive assembly accelerator (PPAA) which can solve not only the functional problems but also improve the shading performance. The register transfer level (RTL) circuit is designed and the detailed approach is presented. The prototype systems are implemented on Xilinx field programmable gate array (FPGA) XC6VLX550T and Altera FPGA EP2C70F896C6. The experimental results show that PPAA can accomplish the assembly tasks correctly and with higher performance of 1.5x and 2.5x of two previous implementations. For the most frequently independent primitives, the PPAA can efficiently enhance the throughput by squeezing out the pipeline bubbles and by balancing the pipeline stages.

Key words:

primitive assembly, parallel accelerator, primitive characteristics, graphics processor