中国邮电高校学报(英文) ›› 2008, Vol. 15 ›› Issue (1): 112-117.doi: 1005-8885 (2008) 01-0112-06

• Microelectronics and Solic State Electronics • 上一篇    下一篇

Ultra-low power S-Boxes architecture for AES

邢冀鹏;邹雪城;郭旭   

  1. Research Center for VLSI and Systems, Department of Electronic Science and Technology, Huazhong University of Science and Technology,
    Wuhan 430074, China
  • 收稿日期:2006-10-25 修回日期:1900-01-01 出版日期:2008-03-31
  • 通讯作者: 邢冀鹏

Ultra-low power S-Boxes architecture for AES

  1. Research Center for VLSI and Systems, Department of Electronic Science and Technology, Huazhong University of Science and Technology,
    Wuhan 430074, China
  • Received:2006-10-25 Revised:1900-01-01 Online:2008-03-31
  • Contact: Xing Jipeng

摘要:

It is crucial to design energy-efficient advanced encryption standard (AES) cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switch- encoder (DSE) architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power: an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 W at 10 MHz using 0.25 m 1.8V UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respectively. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.

关键词:

AES,;S-Boxes,;DSE,;cryptography,;low;power

Abstract:

It is crucial to design energy-efficient advanced encryption standard (AES) cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switch- encoder (DSE) architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power: an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 W at 10 MHz using 0.25 m 1.8V UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respectively. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.

Key words:

AES;S-Boxes;DSE;cryptography;low power

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