中国邮电高校学报(英文) ›› 2007, Vol. 14 ›› Issue (2): 106-111.doi: 1005-8885 (2007) 02-0106-06

• Device • 上一篇    下一篇

High-performance, low-cost joint equalizer and trellis decoder for 1000BASE-T gigabit Ethernet transceive

诸阅;戎蒙恬   

  1. Shanghai Jiao Tong University
  • 收稿日期:2006-09-12 修回日期:1900-01-01 出版日期:2007-06-30

High-performance, low-cost joint equalizer and trellis decoder for 1000BASE-T gigabit Ethernet transceive

ZHU Yue; RONG Meng-tian   

  1. Shanghai Jiao Tong University
  • Received:2006-09-12 Revised:1900-01-01 Online:2007-06-30

摘要:

This article presents an M-algorithm (MA) decoder with 4 survival paths (MA4) for Institute of Electrical and Electronics Engineers (IEEE) 802.3ab 1000BASE-T gigabit Ethernet (GbE) transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and 1 Gb/s throughput in 1.8 V 0.18 μm standard cell complementary metal-oxide-semiconductor (CMOS) process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder (PDFD) with 39% area reduction.

关键词:

1000BASE-T; GbE, M-algorithm;PDFD;look-ahead technology

Abstract:

This article presents an M-algorithm (MA) decoder with 4 survival paths (MA4) for Institute of Electrical and Electronics Engineers (IEEE) 802.3ab 1000BASE-T gigabit Ethernet (GbE) transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and 1 Gb/s throughput in 1.8 V 0.18 μm standard cell complementary metal-oxide-semiconductor (CMOS) process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder (PDFD) with 39% area reduction.

Key words:

1000BASE-T;GbE; M-algorithm;PDFD;look-ahead technology

中图分类号: