Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

doi:10.19682/j.cnki.1005-8885.2018.0015

中国邮电高校学报(英文版) ›› 2018, Vol. 25 ›› Issue (3): 65-70.doi: 10.19682/j.cnki.1005-8885.2018.0015

• Artificial Intelligence • 上一篇下一篇

Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

孙书龙,Linmin

中国科学院上海微系统与信息技术研究所

收稿日期:2016-12-30 修回日期:2018-01-14 出版日期:2018-06-29 发布日期:2018-06-30
通讯作者: 孙书龙 E-mail:ssl2012@mail.ustc.edu.cn

Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

Received:2016-12-30 Revised:2018-01-14 Online:2018-06-29 Published:2018-06-30

摘要/Abstract

摘要： Non-binary low density parity check (NB-LDPC) codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios (SNR) are required. They have better burst error correcting performance, especially with high order Galois fields (GF). A shared comparator(SCOMP) architecture for elementary of check node (ECN)/elementary of variable node (EVN) to reduce decoder complexity is introduced because high complexity of check node (CN) and variable node (VN) prevent NB-LDPC decoder from widely applications. The decoder over GF(16) is based on the extended min-sum (EMS) algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency，the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when shared comparator architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF(64) or GF(256). Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.

关键词: extended min-sum algorithm, non-binary LDPC decoder, shared comparator architecture

Abstract: Non-binary low density parity check (NB-LDPC) codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios (SNR) are required. They have better burst error correcting performance, especially with high order Galois fields (GF). A shared comparator(SCOMP) architecture for elementary of check node (ECN)/elementary of variable node (EVN) to reduce decoder complexity is introduced because high complexity of check node (CN) and variable node (VN) prevent NB-LDPC decoder from widely applications. The decoder over GF(16) is based on the extended min-sum (EMS) algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency，the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when shared comparator architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF(64) or GF(256). Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.

Key words: extended min-sum algorithm, non-binary LDPC decoder, shared comparator architecture

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Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

Low complexity NB-LDPC decoder based on shared comparator architecture for ECN/EVN

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