High performance architecture for unified forward and inverse transform of HEVC

doi:10.1016/S1005-8885(17)60207-3

中国邮电高校学报(英文) ›› 2017, Vol. 24 ›› Issue (3): 16-23.doi: 10.1016/S1005-8885(17)60207-3

• Artificial Intelligence • 上一篇下一篇

High performance architecture for unified forward and inverse transform of HEVC

蒋林

西安邮电大学

收稿日期:2016-09-22 修回日期:2017-04-01 出版日期:2017-06-30 发布日期:2017-06-30
通讯作者: 蒋林 E-mail:1056485294@qq.com
基金资助:
陕西省自然科学基金;陕西省统筹科技创新项目;中国国家自然科学基金

High performance architecture for unified forward and inverse transform of HEVC

Received:2016-09-22 Revised:2017-04-01 Online:2017-06-30 Published:2017-06-30
Supported by:
the Natural Science Foundation of Shaanxi province; National Natural Science Foundation of China

摘要/Abstract

摘要： High efficiency video coding (HEVC) transform algorithm for residual coding uses 2-dimensional (2D) 4×4 transforms with higher precision than H.264’s 4×4 transforms, resulting in increased hardware complexity. In this paper, we present a shared architecture that can compute the 4×4 forward discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) of HEVC using a new mapping scheme in the video processor array structure. The architecture is implemented with only adders and shifts to an area-efficient design. The proposed architecture is synthesized using ISE14.7 and implemented using the BEE4 platform with the Virtex-6 FF1759 LX550T field programmable gate array (FPGA). The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz. The architecture and its implementation are presented in this paper to demonstrate its programmable and high performance.

关键词: HEVC, forward and inverse transform, reconfigurable architecture, video processor array structure

Abstract: High efficiency video coding (HEVC) transform algorithm for residual coding uses 2-dimensional (2D) 4×4 transforms with higher precision than H.264’s 4×4 transforms, resulting in increased hardware complexity. In this paper, we present a shared architecture that can compute the 4×4 forward discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) of HEVC using a new mapping scheme in the video processor array structure. The architecture is implemented with only adders and shifts to an area-efficient design. The proposed architecture is synthesized using ISE14.7 and implemented using the BEE4 platform with the Virtex-6 FF1759 LX550T field programmable gate array (FPGA). The result shows that the video processor array structure achieves a maximum operation frequency of 165.2 MHz. The architecture and its implementation are presented in this paper to demonstrate its programmable and high performance.

Key words: HEVC, forward and inverse transform, reconfigurable architecture, video processor array structure

蒋林 Wang Xingjun, Wu Xin, Deng Junyong, Huang Xingjie. High performance architecture for unified forward and inverse transform of HEVC[J]. JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOM, 2017, 24(3): 16-23.

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High performance architecture for unified forward and inverse transform of HEVC

High performance architecture for unified forward and inverse transform of HEVC

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