中国邮电高校学报(英文) ›› 2016, Vol. 23 ›› Issue (1): 14-21.doi: DOI: 10.1016/S1005-8885(16)60003-1
曾光1,于翠屏1,Li Shu-lan1,刘元安2
摘要：
This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter (DPD). The architecture is implemented on field programmable gate array (FPGA) to compensate for the nonlinearity of the concurrent dual-band power amplifier (PA). This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables (LUTs) sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio (ACPR) is less than
中图分类号:
