Research on physical layer traffic management schemes in serial RapidIO interconnect

doi:10.1016/S1005-8885(10)60029-5

中国邮电高校学报(英文) ›› 2011, Vol. 18 ›› Issue (1): 64-69.doi: 10.1016/S1005-8885(10)60029-5

Research on physical layer traffic management schemes in serial RapidIO interconnect

张勇¹,王勇³,张平²

1. 北京邮电大学
2. 北京邮电大学无线新技术研究所
3.

收稿日期:2010-01-11 修回日期:2010-11-09 出版日期:2011-02-28 发布日期:2011-02-28
通讯作者: 张勇 E-mail: xiazibin@gmail.com
基金资助:
国家级.国家“863计划”项目；国家级.国家自然科学基金;国家级.国家“863计划”项目

Research on physical layer traffic management schemes in serial RapidIO interconnect

Received:2010-01-11 Revised:2010-11-09 Online:2011-02-28 Published:2011-02-28
Contact: ZHANG Yong E-mail: xiazibin@gmail.com

摘要/Abstract

摘要：

A traffic management scheme in serial RapidIO (SRIO) interconnect is proposed to deal with the performance degradation caused by noise and electromagnetic interference (EMI), which is generated by hardly avoidable errors of hardware implementation and tough working environment. The main idea of this scheme includes adaptive speed transition and freeze-acknowledgement (freeze-ACK). Adaptive speed transition can improve throughput and reduce delay in high bit error rate (BER) environment. Simultaneously, freeze-ACK is adopted to conquer frequent usage of feedback channel. Simulation shows that the scheme of combining adaptive speed transition with freeze-ACK offers great performance improvement in SRIO network.

关键词:

serial RapidIO, traffic management, physical layer traffic management, adaptive speed transition, freeze-ACK

Abstract:

Key words:

serial RapidIO, traffic management, physical layer traffic management, adaptive speed transition, freeze-ACK

参考文献

1. Zheng Z X, Zou L Y, Gao J. Power optimization and performance improvement for embedded Ethernet SOC. The Journal of China Universities of Posts and Telecommunications, 2008, 15(2): 102-107

2. Fuller S. Anatomy of a forward-looking open standard [RapidIO]. Computer, 2002, 35(1): 140-141

3. RapidIO Trade Association. RapidIOTM interconnect specification, Part 6: 1x/4x LP-serial physical Layer specification, Version 1.3. 2005

4. Young B. Enhanced LVDS for signaling on the RapidIO interconnect architecture. Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging (EPEP’00), 2000, Oct 23-25, 2000, Scottsdale, AZ , USA. Piscataway, NJ, USA: IEEE, 2000: 17-20

5. Texas Instruments. Implementing serial RapidIO PCB layout on a TMS320C6455 hardware design. [2009-11-20]. http://www.ti.com.

6. Xilinx. Virtex-5 PCB designers guide. [2009-11-20]. http://www.Xilinx.com.

7. Tundra Semiconductor Corporation. Tsi578 hardware manual. [2009-11-20]. http://www.tundra.com

8. Zhang X K, Gao M G, Liu G M. A scalable heterogeneous multiprocessor signal processing system based on the RapidIO interconnect. Proceedings of the IEEE International Symposium on Intelligent Information Technology Application (IITAW'08), Dec 21-22, 2008, Shanghai, China. Piscataway, NJ,USA: IEEE, 2008: 761-764

9. Zhang X K, Liu G M, Gao M G. A high-performance scalable computing system for real-time signal processing applications. Proceedings of the Congress on Image and Signal Processing (CISP’08), May 27-30, 2008, Sanya, China. Piscataway, NJ, USA: IEEE, 2008: 556-560

10. McKenny M, Dines J A B, Harle D. Transporting multiple classes of traffic over a generic routing device: an investigation into the performance of the RapidIO interconnect architecture. Proceedings of the 11th IEEE International Conference on Networks (ICON’03), Sep 28-Oct 1, 2003, Sydney Australia. Piscataway, NJ, USA: IEEE, 2003: 39-44

11. Zhang J, Su H B, Wu Q Z. Research and implement of serial RapidIO based on mul-DSP. Proceedings of the International Conference on Computational Intelligence and Software Engineering (CISE'09), Dec 11-13, 2009, Wuhan , China. Piscataway, NJ, USA: IEEE, 2009: 4p

12. Bueno D, Leko A, Conger C. Simulative analysis of the RapidIO embedded interconnect architecture for real-time, network-intensive applications. Proceedings of the 29th Annual IEEE International Conference on Local Computer Networks (LCN'04), Nov 16-18, 2004, Tampa, FL, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2004: 710-717

13. RapidIO Trade Association. RapidIOTM interconnect specification, Part 1: Input/output logical specification, Version 1.3. 2005

14. RapidIO Trade Association. RapidIOTM interconnect specification, Part 3: Common transport specification, Version 1.3. 2005

15. RapidIO Trade Association. RapidIOTM interconnect specification, Part 4: Physical layer 8/16 LP-LVDS specification, Version 1.3. 2005

16. RapidIO Trade Association. RapidIOTM interconnect specification, Part 9: Flow control logical layer extensions specification, Version 1.3. 2005

17. Fuller S. RapidIO: The embedded system interconnect. Austin, TX, USA: John Wiley, 2007: 249-300

18. Shah S L A, Khanvilkar S, Khokhar A. RapidIO traffic management and flow arbitration protocol. IEEE Communications Magazine, 2006, 44(7): 45-52

19. OPNET Technologies Inc. OPNET product documentation. [2009-11-29]. http://www.opnet.com

Research on physical layer traffic management schemes in serial RapidIO interconnect

Research on physical layer traffic management schemes in serial RapidIO interconnect

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