Area-efficient analog decoder design for low density parity check codes in deep-space applications

doi:10.1016/S1005-8885(17)60225-5

中国邮电高校学报(英文) ›› 2017, Vol. 24 ›› Issue (4): 69-75.doi: 10.1016/S1005-8885(17)60225-5

Area-efficient analog decoder design for low density parity check codes in deep-space applications

赵哲¹,高飞¹,郑浩²

1. 北京理工大学
2. 北京理工大学通信技术研究所

收稿日期:2017-03-29 修回日期:2017-06-15 出版日期:2017-08-30 发布日期:2017-08-30
通讯作者: 赵哲 E-mail:3120130329@bit.edu.cn

Area-efficient analog decoder design for low density parity check codes in deep-space applications

Received:2017-03-29 Revised:2017-06-15 Online:2017-08-30 Published:2017-08-30
Contact: Zhe Zhao E-mail:3120130329@bit.edu.cn

摘要/Abstract

摘要： Area-efficient design methodology is proposed for the analog decoding implementations of the rate-1/2 accumulate repeat-4 jagged-accumulate (AR4JA) low density parity check (LDPC) code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verify the approach is fully integrated in a four-metal double-poly 0.35 μm complementary metal oxide semiconductor (CMOS) technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable for space- and power-constrained spacecraft system.

关键词: low density parity check (LDPC) code, analog decoding, iterative message-passing algorithms, hardware efficient, area utilization

Abstract: Area-efficient design methodology is proposed for the analog decoding implementations of the rate-1/2 accumulate repeat-4 jagged-accumulate (AR4JA) low density parity check (LDPC) code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verify the approach is fully integrated in a four-metal double-poly 0.35 μm complementary metal oxide semiconductor (CMOS) technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable for space- and power-constrained spacecraft system.

Key words: low density parity check (LDPC) code, analog decoding, iterative message-passing algorithms, hardware efficient, area utilization

参考文献

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Area-efficient analog decoder design for low density parity check codes in deep-space applications

Area-efficient analog decoder design for low density parity check codes in deep-space applications

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