Acta Metallurgica Sinica(English letters) ›› 2014, Vol. 21 ›› Issue (3): 85-97.doi: 10.1016/S1005-8885(14)60305-8

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Design and optimization for multiprocessor interactive GPU

邓军勇 LI Tao Jiang Lin HAN Jungang SHEN Xubang   

  1. 1. School of Micro-electronics, Xidian University, Xi’an 710071, China 2. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China
  • 收稿日期:2013-12-30 修回日期:2014-05-09 出版日期:2014-06-30 发布日期:2014-06-30
  • 通讯作者: 邓军勇 E-mail:junyongdeng_arthur@126.com
  • 基金资助:

    This article is supported by the Key National Natural Science Foundation of China under Grant No.61136002, the National Natural Science Foundation of China under Grant No.61272120, and the Natural Science Basic Research Plan in Shaanxi Province of China under Grant No.2013JC2-32.

Design and optimization for multiprocessor interactive GPU

邓军勇 LI Tao Jiang Lin HAN Jungang SHEN Xubang   

  1. 1. School of Micro-electronics, Xidian University, Xi’an 710071, China 2. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China
  • Received:2013-12-30 Revised:2014-05-09 Online:2014-06-30 Published:2014-06-30
  • Supported by:

    This article is supported by the Key National Natural Science Foundation of China under Grant No.61136002, the National Natural Science Foundation of China under Grant No.61272120, and the Natural Science Basic Research Plan in Shaanxi Province of China under Grant No.2013JC2-32.

摘要:

In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit (MIGPU). This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array (FPGA). MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.

关键词:

multiprocessor, graphics processing unit (GPU), performance optimization, parallelism

Abstract:

In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit (MIGPU). This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array (FPGA). MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.

Key words:

multiprocessor, graphics processing unit (GPU), performance optimization, parallelism