| 1. Lee S H H, Chakrabarty K. Test challenges for 3D integrated circuits. IEEE Design and Test of Computers, 2009, 26(5): 26-35
2. Jiang L, Xu Q, Chakrabarty K, et al. Layout-driven test architecture design and optimization for 3-D SoCs under pre-bond test pin-count constraint. Proceedings of the 2009 IEEE/ACM International Conference on Computer Aided Design, Nov 2-5, 2009, San Jose, CA, USA. Piscataway, NJ, USA: IEEE, 2009: 191-196
3. Guibane B, Hamdi B, Bensalem B, et al. A novel efficient TSV built-in test for stacked 3D ICs. Turkish Journal of Electrical Engineering and Computer Sciences, 2018, 26: 1909-1921
4. Pradhan M，Giri C , Rahaman H, et al. Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 2013 IEEE International 3D Systems Integration Conference, Oct 2-4, 2013, San Francisco, USA, IEEE, 2013: 1-5
5. Noia B, Goel S K, Chakrabarty K, et al. Test-architecture optimization for TSV-based 3D stacked ICs. Proceedings of the 15th IEEE European Test Symposium, May 24-28, 2010, Praha, Czech. Piscataway, NJ, USA: IEEE, 2010: 24-29
6. . Aghaee N, Peng Z, Eles P. An integrated temperature-cycling acceleration and test technique for 3D stacked ICs. Proceedings of the 20th Asia and South Pacific Design Automation Conference, Jan 19-22, 2015, Chiba, Japan. Piscataway, NJ, USA: IEEE, 2015: 526-531
7. Noia B, Chakrabarty K, Goel S K, et al. Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30 (11): 1705- 1718
8. Noia B, Chakrabarty K. Design-for-test and test optimization techniques for TSV-based 3D stacked ICs. Berlin, Germany: Springer, 2014
9. Rawat I, Gupta M K, Singh.V. Parallel test scheduling of 3D stacked SoCs with temperature and time constraints. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), 2015, 5(4): 1-13
10. Sheshadri V, Agrawal V D, Agrawal P. Power-aware SoC Ttest optimization through dynamic voltage and frequency scaling. Proceedings of the IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC’13), Oct 7-9, 2013, Istanbul, Turkey. Piscataway, NJ, USA: IEEE, 2013:102-107
11. Anderegg L, Eidenbenz S. Ad hoc-VCG: A truthful and cost-efficient routing protocol for mobile ad hoc networks with selfish agents. Proceedings of the 9th Annual International Conference on Mobile Computing and Networking (MobiCom '03), Sept 14-19, 2003, San Diego, CA, USA. New York, NY, USA: ACM, 2003: 245-259
12. Nash J F. Non-cooperative games. Annals of Mathematics, 1951, (2): 286-295
13. Marinissen E J, Iyengar V, Chakrabarty K. A set of benchmarks for modular testing of SOCs. Proceedings of the 2002 IEEE International Test Conference (ITC'02), Oct 7-10, 2002, Baltimore, MD, USA. Piscataway, NJ, USA: IEEE, 2002: 519-528
14. Xu Q, Nicolici N. Resource-constrained system-on-a-chip test: A survey. IEE Proceedings: Computers and Digital Techniques, 2005, 152(1): 67-81
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