1. Declercq D, Fossorier M. Decoding algorithms for nonbinary LDPC codes over GF(q). IEEE Transactions on Communications, 2007, 55(4): 633-643
2. Davey M C, MacKay D. Low-density parity check codes over GF (q). IEEE Communications Letters, 1998, 2(6) : 165-167
3. Savin V. Min-max decoding for non-binary LDPC codes. Proceedings of the 2008 IEEE International Symposium on Information Theory, Jul 6-11, 2008, Toronto, Canada. Piscataway, NJ, USA: IEEE, 2008: 960-964
4. Zhang X M, Cai F. Reduced-complexity decoder architecture for non-binary LDPC Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(7): 1229-1238
5. Spagnol C, Marnane W, Popovici E. FPGA implementations of LDPC over GF (2m) decoders. Proceedings of the 2007 IEEE Workshop on Signal Processing Systems, Oct 17-19, 2007, Shanghai, China. Piscataway, NJ, USA: IEEE, 2007: 273-278
6. Boutillon E, Conde-Canencia L. Bubble check: A simplified algorithm for elementary check node processing in extended min-sum non-binary LDPC decoders. Electronics Letters, 2010, 46(9): 633-634
7. Voicila A, Declercq D, Verdier F, et al. Low complexity decoding for non-binary LDPC codes in high order fields. IEEE Transactions on Communications, 2010, 58((5): 1365-1375
8. HuangQ, Diao Q J, Lin S, et al. Cyclic and quasi-cyclic LDPC codes on constrained parity-check matrices and their trapping sets. IEEE Transactions on Information Theory, 2012, 58(5): 2648-2671
9. Chavet C, Coussy P. A memory mapping approach for parallel interleaver design with multiple read and write accesses. Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS’10), May 30- Jun 2, Paris, France. Piscataway, NJ, USA: IEEE, 2010: 3168-3171
10. Boutillon E, Conde-Canencia L, Ghouwayel A A. Design of a GF(64)-LDPC decoder based on the EMS algorithm. IEEE Transactions on Circuits and SystemsI: Regular Papers, 2013, 60(10) : 2644-2655
11. Peng R R, Chen R R. Design of nonbinary quasi-cyclic LDPC cycle codes. Proceedings of the 2013 IEEE Information Theory Workshop (ITW'07), Sept 2-6, 2007, Tahoe City, CA, USA. Piscataway, NJ, USA: IEEE, 2007: 13-18
12. Sarkis G, Gross W J. Efficient stochastic decoding of non-binary LDPC codes with degree-two variable nodes. IEEE Communications Letters, 2012, 16( 3): 389-391
13. Sun S L, Lin M. High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm. IEICE Electronics Express, 2016, 13(17): 20160653/1-8
14. Tao Y Y, Park Y S, Zhang Z Y. High-throughput architecture and implementation of regular (2, dc) non-binary LDPC decoders. Proceedings of the 2012 IEEE International Symposium on Circuits and Systems (ISCAS’12), May 20-23, 2012, Seoul, Republic of Korea. Piscataway, NJ, USA: IEEE, 2012: 2625-2628
15. Lacruz j O, García-Herrero F, Canet M J, et al. A 630 Mbps non-binary LDPC decoder for FPGA Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS’15), May 24-27, 2015, Lisbon, Portugal. Piscataway, NJ, USA: IEEE, 2015: 1989-1992 |