JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOM ›› 2016, Vol. 23 ›› Issue (1): 14-21.doi: DOI: 10.1016/S1005-8885(16)60003-1
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Supported by:
The National Basic Research Program of China;The National Natural Science Foundation of China for the Major Equipment Development
Abstract:
This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter (DPD). The architecture is implemented on field programmable gate array (FPGA) to compensate for the nonlinearity of the concurrent dual-band power amplifier (PA). This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables (LUTs) sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio (ACPR) is less than 59 dBc and normalized mean square error (NMSE) is around 62dB for lower sideband (LSB) and 63dB for upper sideband (USB).
Key words:
field programmable gate array (FPGA)
CLC Number:
TN722.7+5
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URL: https://jcupt.bupt.edu.cn/EN/DOI: 10.1016/S1005-8885(16)60003-1
https://jcupt.bupt.edu.cn/EN/Y2016/V23/I1/14
