A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

doi:10.1016/S1005-8885(11)60237-9

Acta Metallurgica Sinica(English letters) ›› 2012, Vol. 19 ›› Issue (1): 124-128.doi: 10.1016/S1005-8885(11)60237-9

• Others • Previous Articles

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China

Received:2011-06-27 Revised:2011-10-26 Online:2012-02-28 Published:2012-02-21
Contact: CHEN Ying-mei E-mail: njcym@seu.edu.cn
Supported by:
This work was supported by the National Natural Science Foundation of China (60976029).

Abstract

Abstract:

A fully integrated 40 Gbit/s optical receiver analog front-end (AFE) including a transimpedance amplifier (TIA) and a limiting amplifier (LA) for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode (RGC) configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV(p p). Simulation results show that the receiver AFE provides conversion gain of up to 83 and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 ?A(rms).

Key words:

optical receiver, transimpedance amplifier, limiting amplifier, active feedback, negative capacitance, inductor peaking

References

1. Tran H, Pera F, McPherson D S, et al. 6 kΩ 43 Gbit/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range. IEEE Journal of Solid-State Circuits, 2004, 39(10): 1680-1689

2. Hauptmann S, Schoeniger D, Eickhoff R. A 40 Gbit/s transimpedance amplifier in 0.25 μm SiGe technology with ultra low power consumption. Proceedings of the 17th International Conference on Microwaves, Radar and Wireless Communications (MIKON’08), May 19-21, 2008, Krakow, Poland. Piscataway, NJ, USA: IEEE, 2008: 4p

3. Knochenhauer C, Sedighi B, Ellinger F. 40 Gbit/s transimpedance amplifier with high linearity range in 0.13 μm SiGe BiCMOS. Electronics Letters, 2011, 47(10): 605-606

4. Amid S B, Plett C, Schvan P. Fully differential, 40 Gb/s regulated cascode transimpedance amplifier in 0.13 μm SiGe BiCMOS technology. Proceedings of the IEEE Bipolar/BiCMOS circuits and Technology Meeting (BCTM’10), Oct 4-6, 2010, Austin, TX, SA. Piscataway, NJ, USA: IEEE, 2010: 33-36

5. Knochenhauer C, Hauptmann S, Scheytt J C. A jitter-optimized differential 40 Gbit/s transimpedance amplifier in SiGe BiCMOS. IEEE Transactions on Microwave Theory and Techniques, 2010, 58(10): 2538-2548

6. Dutta A K, Takechi M, Virk R S. 40 Gb/s postamplifier and PIN/preamplifier modules for next generation optical front-end systems. Journal of Lightwave Technology, 2002, 20(12): 2229-2238

7. Liao C F, Liu S I. 40 Gbit/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 2008, 43(3): 642-655

8. Kromer C, Sialm G, Erni D, et al. A 40 Gbit/s optical receiver in 80 nm CMOS for short-distance high-density interconnects. Proceedings of the IEEE Asian Solid-State Circuits Conference(ASSCC’06), Nov 13-15, 2006, Hangzhou, China.Piscataway, NJ, USA: IEEE, 2006: 395-398

9. Bashiri S, Plett C, Aguirre J, et al. A 40 Gbit/s transimpedance amplifier in 65 nm CMOS technology. Proceedings of the International Symposium on Circuits and Systems (ISCAS’10), May 30-Jun 3, 2010, Paris, France. New York, NY, USA: IEEE, 2010: 757-760

10. Kim J, Buckwalter J F. A 40 Gbit/s optical transceiver front-end in 45 nm SOI CMOS technology. Proceedings of the 2010 IEEE Custom Integrated Circuits Conference (CICC’10), Sep 19-22, 2010, San Jose, CA, USA. Piscataway, NJ, USA: IEEE, 2010: 4p

11. Park S M, Yoo H J. 1.25 Gbit/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications. IEEE Journal of Solid-State Circuits, 2004, 39(1): 112-121

12. Kromer C, Sialm G, Morf T, et al. A low-power 20 GHz 52 dBΩ transimpedance amplifier in 80 nm CMOS. IEEE Journal of Solid-State Circuits, 2004, 39(6): 885-894

13. Huang H Y, Chien J C, Lu L H. A 10 Gbit/s inductorless CMOS limiting amplifier with third-order interleaving active feedback. IEEE Journal of Solid-State Circuits, 2007, 42(5): 1111-1120

14. Galal S, Razavi B. 10 Gbit/s limiting amplifier and laser/modulator driver in 0.18 μm CMOS technology. IEEE Journal of Solid-State Circuits, 2003, 38(12): 2138-2146

Metrics

Comments

Copyright © 2020 The Journal of China Universities of Posts and Telecommunications
　 Adress: P.O. Box 231,Beijing University of Posts and Telecommunications,10 Xi Tucheng Road,Beijing 100876,P.R.China　Post Code: 100081
Tel：86-010-62282493　Fax： 86-010-62283461　E-mail: jchupt@bupt.edu.cn
Support by: Beijing Magtech Co.Ltd

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

Knowledge

Cited

Abstract

Cite this article

share this article

References

Related Articles 0

Recommended Articles

Metrics

Comments