Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

doi:10.1016/S1005-8885(08)60232-0

Acta Metallurgica Sinica(English letters) ›› 2009, Vol. 16 ›› Issue (3): 89-94.doi: 10.1016/S1005-8885(08)60232-0

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Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

LI Zhen-rong, ZHUANG Yi-qi, ZHANG Chao, JIN Gang

Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071, China

Received:1900-01-01 Revised:1900-01-01 Online:2009-06-30
Contact: LI Zhen-rong

Abstract

Abstract:

A low-power and low-cost advanced encryption standard (AES) coprocessor is proposed for Zigbee system-on-a-chip (SoC) design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine (FSM) and clock gating (CG) technologies. Based on SMIC 0.18 complementary metal oxide semiconductor (CMOS) technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 , and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.

Key words:

Zigbee;AES;architecture;encryption;decryption;application specific integrated circuit (ASIC)

LI Zhen-rong, ZHUANG Yi-qi, ZHANG Chao, JIN Gang. Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system[J]. Acta Metallurgica Sinica(English letters), 2009, 16(3): 89-94.

References

1. ZigBee Alliance. ZigBee Specification Version 1.0. San Ramon, CA, USA: ZigBee Standards Organization, 2004

2. IEEE 802.15.4—2006. IEEE standard for information technology—Telecommunications and information exchange between system—Local and metropolitan area networks specific requirements, Part 15.4: Wireless MAC and physical layer (PHY) specifications for low-rat wireless personal area networks (LR-WPANs). 2006

3. Federal Information Processing Standards (FIPS) 197. Specification for the advanced encryption standard (AES). 2001

4. Kosaraju N M, Varanasi M, Mohanty S P. A high-performance VLSI architecture for advanced encryption standard (AES) algorithm. Proceedings of 19th International Conference on VLSI Design, Held with the 5th International Conference on Embedded Systems and Design, Jan 3-7, 2006, Hyderabad, India. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 4

5. Alam M, Ray S, Mukhopadhayay D, et al. an area optimized reconfigurable encryptor for AES-rijndael. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Apr 16-20, 2007. Nice, France. Piscataway, NJ, USA: IEEE, 2007: 1- 6

6. Huang Y J, Lin Y S, Hung K Y, et al. Efficient implementation of AES IP. Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, Dec 4-7, 2006, Singapore. Piscataway, NJ ,USA: IEEE, 2006: 1418-1421

7. Zhao J, Zeng X Y, Han J, et al. Very low-cost VLSI implementation of AES Algorithm. Proceedings of IEEE Asian Solid-State Circuits Conference, Nov 13-15, 2006, Hangzhou, China. Piscataway, NJ, USA: IEEE, 2006: 223-226

8. Iyer N C, Anandmohan P V, Poornaiah D V, et al. High throughput, low cost, fully pipelined architecture for AES crypto chip. Proceedings of 2006 Annual IEEE India Conference, Sep 15-17, 2006, New Delhi, India. Piscataway, NJ, USA: IEEE, 2006: 1-6

9. Huang C W, Chang C J, Lin M Y, et al. Compact FPGA implementation of 32-bits AES algorithm using block RAM Proceedings of 2007 IEEE Region 10 Conference, Oct 30-Nov 2, 2007 Teipei, China. Piscataway, NJ, USA: IEEE, 2007: 1-4

10. Li H. Efficient and flexible architecture for AES. IEE Proceedings: Circuits, Devices and Systems, 2006, 153(6): 533-538

11. Fan C P, Hwang J K. Implementations of high throughput sequential and fully pipelined AES processors on FPGA. Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems, Nov 28-Dec 1, 2007, Xiamen, China. Piscataway, NJ, USA: IEEE, 2007: 353-356

12. Salomon D. Data privacy and security. Berlin, Germany: Springer, 2003

13. Fischer V, Drutarovsky M, Chodowiec P, et al. InvMixColumn decomposition and multilevel resource sharing in AES implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(8): 989-992

14. Nakajima M, Yamamoto T, Yamasaki M, et al. Low power techniques for mobile application SoCs based on integrated platform “UniPhier” Proceedings of Asia and South Design Automation Conference, Jan 23-26, 2007, San Diego, CA, USA. Piscataway, NJ, USA: IEEE, 2007: 649-653

15. Babighian P, Benini L, Macii E. A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(1): 29-42

16. Kothari N B, Sudarshan T S B, Gurunarayanan S, et al. SOC design of a low power wireless sensor network node for Zigbee systems. Proceedings of International Conference on Advanced Computing and Communications, Dec 20-23, 2006, Surathka, India. Piscataway, NJ, USA: IEEE, 2006: 462-466

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Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

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