Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

doi:10.1016/S1005-8885(08)60232-0

中国邮电高校学报(英文) ›› 2009, Vol. 16 ›› Issue (3): 89-94.doi: 10.1016/S1005-8885(08)60232-0

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

李振荣,庄奕琪,张超,靳刚

Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071, China

收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-06-30
通讯作者: 李振荣

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

LI Zhen-rong, ZHUANG Yi-qi, ZHANG Chao, JIN Gang

Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi’an 710071, China

Received:1900-01-01 Revised:1900-01-01 Online:2009-06-30
Contact: LI Zhen-rong

摘要/Abstract

摘要：

A low-power and low-cost advanced encryption standard (AES) coprocessor is proposed for Zigbee system-on-a-chip (SoC) design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and decryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine (FSM) and clock gating (CG) technologies. Based on SMIC 0.18 complementary metal oxide semiconductor (CMOS) technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 , and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.

关键词:

Zigbee,;AES,;architecture,;encryption,;decryption,;application;specific;integrated;circuit;(ASIC)

Abstract:

Key words:

Zigbee;AES;architecture;encryption;decryption;application specific integrated circuit (ASIC)

LI Zhen-rong, ZHUANG Yi-qi, ZHANG Chao, JIN Gang. Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system[J]. Acta Metallurgica Sinica(English letters), 2009, 16(3): 89-94.

参考文献

1. ZigBee Alliance. ZigBee Specification Version 1.0. San Ramon, CA, USA: ZigBee Standards Organization, 2004

2. IEEE 802.15.4—2006. IEEE standard for information technology—Telecommunications and information exchange between system—Local and metropolitan area networks specific requirements, Part 15.4: Wireless MAC and physical layer (PHY) specifications for low-rat wireless personal area networks (LR-WPANs). 2006

3. Federal Information Processing Standards (FIPS) 197. Specification for the advanced encryption standard (AES). 2001

4. Kosaraju N M, Varanasi M, Mohanty S P. A high-performance VLSI architecture for advanced encryption standard (AES) algorithm. Proceedings of 19th International Conference on VLSI Design, Held with the 5th International Conference on Embedded Systems and Design, Jan 3-7, 2006, Hyderabad, India. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 4

5. Alam M, Ray S, Mukhopadhayay D, et al. an area optimized reconfigurable encryptor for AES-rijndael. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Apr 16-20, 2007. Nice, France. Piscataway, NJ, USA: IEEE, 2007: 1- 6

6. Huang Y J, Lin Y S, Hung K Y, et al. Efficient implementation of AES IP. Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, Dec 4-7, 2006, Singapore. Piscataway, NJ ,USA: IEEE, 2006: 1418-1421

7. Zhao J, Zeng X Y, Han J, et al. Very low-cost VLSI implementation of AES Algorithm. Proceedings of IEEE Asian Solid-State Circuits Conference, Nov 13-15, 2006, Hangzhou, China. Piscataway, NJ, USA: IEEE, 2006: 223-226

8. Iyer N C, Anandmohan P V, Poornaiah D V, et al. High throughput, low cost, fully pipelined architecture for AES crypto chip. Proceedings of 2006 Annual IEEE India Conference, Sep 15-17, 2006, New Delhi, India. Piscataway, NJ, USA: IEEE, 2006: 1-6

9. Huang C W, Chang C J, Lin M Y, et al. Compact FPGA implementation of 32-bits AES algorithm using block RAM Proceedings of 2007 IEEE Region 10 Conference, Oct 30-Nov 2, 2007 Teipei, China. Piscataway, NJ, USA: IEEE, 2007: 1-4

10. Li H. Efficient and flexible architecture for AES. IEE Proceedings: Circuits, Devices and Systems, 2006, 153(6): 533-538

11. Fan C P, Hwang J K. Implementations of high throughput sequential and fully pipelined AES processors on FPGA. Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems, Nov 28-Dec 1, 2007, Xiamen, China. Piscataway, NJ, USA: IEEE, 2007: 353-356

12. Salomon D. Data privacy and security. Berlin, Germany: Springer, 2003

13. Fischer V, Drutarovsky M, Chodowiec P, et al. InvMixColumn decomposition and multilevel resource sharing in AES implementations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(8): 989-992

14. Nakajima M, Yamamoto T, Yamasaki M, et al. Low power techniques for mobile application SoCs based on integrated platform “UniPhier” Proceedings of Asia and South Design Automation Conference, Jan 23-26, 2007, San Diego, CA, USA. Piscataway, NJ, USA: IEEE, 2007: 649-653

15. Babighian P, Benini L, Macii E. A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(1): 29-42

16. Kothari N B, Sudarshan T S B, Gurunarayanan S, et al. SOC design of a low power wireless sensor network node for Zigbee systems. Proceedings of International Conference on Advanced Computing and Communications, Dec 20-23, 2006, Surathka, India. Piscataway, NJ, USA: IEEE, 2006: 462-466

[1]	Cheng Yi, Zhao Yan, Yin Peiwen. Radar false alarm plots elimination based on multi-feature extraction and classification[J]. 中国邮电高校学报(英文版), 2024, 31(1): 83-92.
[2]	孟慧任利娜赵宗渠. Identity-based proxy re-encryption scheme from RLWE assumption with ciphertext evolution[J]. 中国邮电高校学报(英文版), 2023, 30(5): 51-60.
[3]	Li Yajie, Zhang Jie. Artificial intelligence for optical transport networks: architecture, application and challenges [J]. 中国邮电高校学报(英文版), 2022, 29(6): 3-17.
[4]	Shi Jinjing, Wang Wenxuan, Xiao Zimeng, Mu Shuai, Li Qin. Quantum classifier with parameterized quantum circuit based on the isolated quantum system[J]. 中国邮电高校学报(英文版), 2022, 29(4): 21-31.
[5]	Liu Guangyi, Deng Juan, Zheng Qingbi, Li Gang, Sun Xin, Huang Yuhong. Native intelligence for 6G mobile network: technical challenges, architecture and key features[J]. 中国邮电高校学报(英文版), 2022, 29(1): 27-40.
[6]	Han Gang, Xing Qixuan, Zhang Yinghui. Fine-grained cooperative access control scheme with hidden policies[J]. 中国邮电高校学报(英文版), 2021, 28(6): 13-25.
[7]	宋文鹏李鸣刘百祥. Trusted data access and authorization protocol [J]. 中国邮电高校学报(英文版), 2021, 28(5): 18-26.
[8]	敦书波金秋延毕凌宇王紫任谢军. Behavior modeling on the PIM performance in connectors using FEA method and circuit simulation [J]. 中国邮电高校学报(英文版), 2021, 28(1): 87-93.
[9]	商玉洁张乐友高小旭. Continual auxiliary leakage-resilient attribute-based broadcast encryption with constant size ciphertexts [J]. 中国邮电高校学报(英文版), 2020, 27(4): 69-82.
[10]	周国强, 范译, ZHANG Shuai WANG Yilun DAI Gui-lan. IDL: Evaluating software quality based on PageRank algorithm[J]. 中国邮电高校学报(英文版), 2020, 27(1): 10-25.
[11]	Yang Tao, Yan Yonghong, Zhang Yue, Guo Huijuan, Zhu Yongyuan, Huang Wei, . Single-Cavity triangular substrate integrated waveguide bandpass filter with complementary triangular split ring resonator[J]. 中国邮电高校学报(英文版), 2019, 26(5): 94-98.
[12]	Zhang Zhao, Zhang Yong, Teng Ying lei, Guo Da, Deng Hai qin. Adaptive transfer learning framework for dense prediction of human activity recognition[J]. 中国邮电高校学报(英文版), 2019, 26(5): 1-10.
[13]	Deng Junyong, Liu Yang, Xie Xiaoyan. Performance Characterization of Illumination Algorithms for Reconfigurable Graphics Processor[J]. 中国邮电高校学报(英文版), 2019, 26(5): 60-71.
[14]	崔义垒张乐友. Privacy preserving ciphertext-policy attribute-based broadcast encryption in smart city[J]. 中国邮电高校学报(英文版), 2019, 26(1): 21-31.
[15]	张金玲吕蕾. Integrated Trojan detecting model based on period feature statistics[J]. 中国邮电高校学报(英文版), 2019, 26(1): 32-39.

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

PDF

可视化

被引次数

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

编辑推荐

Metrics

本文评价