Acta Metallurgica Sinica(English letters) ›› 2015, Vol. 22 ›› Issue (2): 96-100.doi: 10.1016/S1005-8885(15)60645-8

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Design of 25 Gbit/s half-rate CDR with 1:2 demultiplexer for 100 GbE optical interconnects


  • Received:2014-09-02 Revised:2015-01-17 Online:2015-04-30 Published:2015-04-22
  • Supported by:

    National Natural Science Foundation of China

Abstract: A 25 Gbit/s clock and data recovery (CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethernet (100 GbE) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company (TSMC) 65nm complementary metal-oxide-semiconductor (CMOS) technology. A novel quadrature voltage-controlled-oscillator (QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to pseudorandom bit sequence (PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW (excluding output buffers).

Key words: CDR, bang-bang phase detector, quadrature voltage-controlled oscillator (QVCO), 100 GbE