1.    Do A T, Chen S C, Kong Z H,et al. A high speed low power CAM with a parity bit and power-gated ML sensing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2013, 21(1): 151-156

  2.    Frontini L, Shojaii S, Stabile A, et al. A new XOR-based content addressable memory architecture. Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS’12), Dec 9-12, 2012, Seville Spain. Piscataway, NJ, USA: IEEE, 2012: 701-704

  3.    Pagiamtzis K, Sheikholeslami A. A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme. IEEE Journal of Solid-State Circuits, 2004, 39(9): 1512-1519

  4.    Kim Y D, Ahn H S, Kim S, et al. A high-speed range-matching TCAM for storage-ef?cient packet classi?cation. IEEE Transactions on Circuits and Systems—I: Regular Papers, 2009, 56(6): 1221-1230

  5.    Yang B D, Lee Y K, Sung S W, et al. A low power content addressable memory using low swing search lines.IEEE Transactions on Circuits and Systems—I: Regular Papers, 2011, 58(12): 2849-2858

  6.    Pagiamtzis K, Sheikholeslami A. Content-addressable memory (CAM) circuits and architectures: A tutorial and survey. IEEE Journal of Solid-State Circuits, 2006, 41(3): 712-727 

  7.    Ali S I, Islam M S. A high-speed and low-power ternary CAM design using match-line segmentation and feedback in sense amplifiers. Proceedings of the 13th International Conference on Computer and Information Technology (ICCIT’10), Dec 23-25, 2010, Dhaka, Bangladesh. Piscataway, NJ, USA: IEEE, 2010: 221-226

  8.    Ng K F. Novel low power CAM architecture. Thesis. Rochester, NY, USA: Rochester Institute of Technology, 2008

  9.    Chang Y J, Liao Y H. Hybrid-type CAM design for both power and performance efficiency. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2008,16(8): 965-974

10.    Chang Y J, Liao Y H, Ruan S J. Improve CAM power efficiency using decoupled match line scheme. Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exhibition (DATE’07), Apr 16-20, 2007, Nice, France. Piscataway, NJ,USA: IEEE, 2007: 6p

11.    Nagarjuna V, Kittur H M. Low power, low area and high performance hybrid type dynamic CAM design. Proceedings of the 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN’11), Jul 21-22, 2011, Thuckalay, India. Piscataway, NJ, USA: IEEE, 2011: 430-435