1. Frequency agile jitter measurement system. Application Note 1267. Santa Clara, CA, USA: Agilent Technologies. 2005
2. Razavi B. Design of integrated circuits for optical communications. New York, NY, USA: McGraw Hill, 2003
3. Greshishchev Y M, Schvan P. SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. IEEE Journal of Solid-State Circuits, 2000, 35(9): 1353-1359
4. ITU-T G.8251. The control of jitter and wander within the optical transport network. 2001
5. Lee T, Bulzacchelli J. A 155-MHz clock recovery delay-and phase-locked loop. IEEE Journal of Solid-State Circuits, 1992, 27(12): 1736-1746
6. Dalton D, Chai K, Evans E, et al. A 12.5 Mb/s to 2.7Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. IEEE Journal of Solid-State Circuits, 2005, 40(12): 2713-2725
7. Kenney J, Dalton D, Eskiyerli M, et al. A 9.95 to 11.1 Gb/s XFP transceiver in 0.13-µm/spl µm/m CMOS. Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC’06), Feb 6-9, 2006, San Francisco, CA, USA. Piscataway, NJ, USA: IEEE , 2006: 864-873
8. Liang C F, Hwu S C, Liu S I. A jitter-tolerance-enhanced CDR using a GDCO-based phase detector. IEEE Journal of Solid-State Circuits, 2008, 43(5): 1217-1226 |