To tackle the challenge of applying convolutional neural network (CNN) in field-programmable gate array (FPGA) due to its computational complexity, a high-performance CNN hardware accelerator based on Verilog hardware description language was designed, which utilizes a pipeline architecture with three parallel dimensions including input channels, output channels, and convolution kernels. Firstly, two multiply-and-accumulate (MAC) operations were packed into one digital signal processing (DSP) block of FPGA to double the computation rate of the CNN accelerator. Secondly, strategies of feature map block partitioning and special memory arrangement were proposed to optimize the total amount of off-chip access memory and reduce the pressure on FPGA bandwidth. Finally, an efficient computational array combining multiplicative-additive tree and Winograd fast convolution algorithm was designed to balance hardware resource consumption and computational performance. The high parallel CNN accelerator was deployed in ZU3EG of Alinx, using the YOLOv3-tiny algorithm as the test object. The average computing performance of the CNN accelerator is 127.5 giga operations per second (GOPS). The experimental results show that the hardware architecture effectively improves the computational power of CNN and provides better performance compared with other existing schemes in terms of power consumption and the efficiency of DSPs and block random access memory (BRAMs).

The research purpose of this paper is focused on investigating the performance of extra-large scale massive multiple-input multiple-output ( XL-MIMO) systems with residual hardware impairments. The closed-form expression of the achievable rate under the match filter (MF) receiving strategy was derived and the influence of spatial non-stationarity and residual hardware impairments on the system performance was investigated. In order to maximize the signal-to-interference-plus-noise ratio ( SINR ) of the systems in the presence of hardware impairments, a hardware impairments-aware minimum mean squared error (HIA-MMSE) receiver was proposed. Furthermore, the stair Neumann series approximation was used to reduce the computational complexity of the HIA-MMSE receiver, which can avoid matrix inversion. Simulation results demonstrate the tightness of the derived

analytical expressions and the effectiveness of the low complexity HIA-MMSE (LC-HIA-MMSE) receiver.

The manifold matrix of the received signals can be destroyed when the array is with the gain and phase errors,which will affect the performance of the traditional direction of arrival (DOA) estimation approaches. In this paper,a novel active array calibration method for the gain and phase errors based on a cascaded neural network(GPECNN) was proposed. The cascaded neural network contains two parts: signal-to-noise ratio ( SNR) classification network and two sets of error estimation subnetworks. Error calibration subnetworks are activated according to the output of the SNR classification network, each of which consists of a gain error estimation network(GEEN) and a phase error estimation network (PEEN), respectively. The disadvantage of neural network topology architecture is changing when the number of array elements varies is addressed by the proposed group calibration strategy. Moreover, due to the data characteristics of the input vector, the cascaded neural network can be applied to arrays with arbitrary geometry without repetitive training. Simulation results demonstrate that the GPECNN not only achieves a better balance between calibration performance and calibration complexity than other methods but also can be applied to arrays with different numbers of sensors or different shapes without repetitive training.